This invention relates generally to integrated circuit packaging. More particularly, the invention relates to interconnected and leadless packaging of semiconductor devices.
Integrated circuits may be contained in a variety of different packages before they are integrated into portions of larger electronic systems. The packages are generally comprised of one or more semiconductor chips encapsulated in a packaging material. In the case of packages containing several chips, the chips are interconnected to permit the chips to cooperatively perform a variety of tasks. In addition to the interconnections between the chips within the package, other connections generally extend from the package to permit the integrated circuit to interact with other portions of a larger electronic system. The individual chips may be arranged in the package in a planar configuration with electrical interconnections extending between the chips, but increasingly, the individual chips are arranged in a vertical stack, with the interconnections extending between the chips comprising the stack. A stacked wafer-level package has numerous advantages over the planar arrangement, including reduced interconnection lengths, faster processing times, and substantial reductions in the size and weight of the package.
FIG. 1 is a partial cross sectional view showing a vertically stacked semiconductor package 10 according to the prior art. The package 10 generally includes a substrate 16 that supports a first semiconductor chip 14, which is retained on the substrate 16 by an adhesive layer 18. The adhesive layer 18 is generally comprised of an adhesive compound having a high dielectric strength to prevent electrical communication between the chip 14 and the substrate 16. The chip 14 also generally includes one or more bond pads 15 that are electrically coupled to the circuits formed on the chip 14, which form at least a portion of the signal input and/or signal output locations for the chip 14. A second chip 12 is positioned on the chip 14, and is similarly retained on the chip 14 by an adhesive layer 19. The second chip 12 also includes one or more bond pads 11 that are coupled to the circuits formed on the chip 12, and similarly form at least a portion of the signal input and/or signal output locations for the chip 12. Electrical communication between the chip 12 and the chip 14 is obtained through one or more electrically conductive bonding wires 13 that couple the bond pad 11 on the chip 12 to the bond pad 15 on the chip 14. The bonding wires 13 are generally comprised of gold or aluminum, and may be attached to the bond pads 11 and 15 by spot welding, soldering, or by various conductive adhesive compounds. The bonding wires 13 then generally proceed away from the package 10 to provide an electrical connection to other portions of a larger electronic system (not shown).
The prior art semiconductor package 10 shown in FIG. 1 has numerous drawbacks, however. For example, the bonding wire 13 generally has a relatively long physical length in order to establish the required electrical interconnections between the bond pads 11 and 15. The long physical length of bonding wire 13 may therefore lead to increased signal propagation delays between the chips 12 and 14. Moreover, as the length of the bonding wire 13 increases, undesirable effects stemming from parasitic capacitance and/or inductance introduced by the bonding wire 13 also increase. Other shortcomings associated with the package 10 may include the reflection of at least part of the signal transmitted along the bonding wire 13 resulting from impedance discontinuities along the bonding wire 13, or at the connection interface between the bonding wire 13 and the bond pads 11 and 15. Still further, as the length of the bonding wire 13 increases, the bonding wire 13 becomes increasingly susceptible to electromagnetic interference since the bonding wire 13 may act as an antenna. Still other drawbacks are present in prior art package 10. For instance, the size of the bond pads 11 and 15 formed on the chips 12 and 14 must generally be relatively large to accommodate the connections formed with the bonding wire 13, which generally limits either the number of input and output locations, or the number of circuits that may be formed on the chips 12 and 14. Moreover, since the bond pads 11 and 15 are generally comprised of gold, the relatively large bond pad areas require additional amounts of this material, which increases the cost of each unit.
Other prior art packaging methods mitigate some of the drawbacks associated with the use of bonding wire interconnections, as described above, but introduce still other drawbacks. For example, tape automated bonding (TAB) methods may be used to establish the interconnections between vertically stacked semiconductor chips. In TAB, metallic interconnection traces are formed on a multi-layer polymer tape (not shown). The polymer tape is positioned adjacent to the chips 12 and 14 with traces and bonding locations pre-formed on the tape that correspond to the bond pads 11 on the chip 12, and the bond pads 15 on the chip 14. The bonding locations on the tape are then attached to the bond pads 11 and 15 on the chips 12 and 14 using conventional joining techniques such as reflow soldering or conductive adhesives. Although TAB allows the bond pads 11 and 15 on the chips 12 and 14 to be spaced at closer intervals than is generally achievable using the foregoing bonding wire method, each chip must generally have its own tape that is individually patterned to conform to the bonding pad arrangements on the chips that are to be interconnected. Consequently, the time and cost associated with the design and fabrication of bonding tapes that are individually configured for each bonding requirement renders TAB methods suitable only to applications where large production quantities of semiconductor packages are anticipated.
The xe2x80x9cflip-chipxe2x80x9d method represents still another prior art semiconductor packaging method, which permits the bond pads on adjacent chips to be connected without the use of a discrete interconnecting elements, as employed in the foregoing bonding wire method, or in TAB. In the xe2x80x9cflip chipxe2x80x9d method, the contact pads of a chip are generally wetted with a reflowable material, such as a solder alloy. The chip is then brought into facial contact with an adjacent chip or substrate that has a corresponding set of bond pads. Reflowing the solder alloy in a furnace then electrically and mechanically joins the chips. Although the foregoing method eliminates many of the drawbacks associated with the wire bonding and TAB interconnection methods, other drawbacks are introduced. For example, the chips thus joined may exhibit significantly different rates of thermal expansion, which may lead to bonding failure between the chips. This shortcoming may be further exacerbated by the degradation of heat conduction through the chip stack that is due to an increase in the thermal resistance between the chips. Additionally, since the connections are formed between the chips, a visual inspection of the bond integrity is generally not possible.
Accordingly, there is a pronounced need for an interconnection apparatus and method for semiconductor packages comprised of vertical chip stacks that permits relatively short interconnecting lengths to extend between chip bonding pads that are patterned on the chips at relatively high densities, while avoiding the thermal incompatibility difficulties present in prior art methods, which is easily adaptable to small as well as larger production runs of semiconductor packages.
The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first semiconductor chip with a second semiconductor chip positioned on the first chip to form a vertically stacked package. Each semiconductor chip further includes a plurality of bond pads disposed on an active surface of the chips that are electrically coupled to the active elements formed within each chip. Interconnections between the bond pads on each chip are formed by metallized layers disposed on the package that extend between corresponding bond pads and join a plurality of castellations disposed along sides of the package to form a plurality of leadless input/output locations for the package. In one aspect of the invention, the castellations include generally planar metallized portions extending downwardly to a lower surface of the package. In another aspect, the castellations include semi-cylindrical metallized portions that project inwardly into sides of the package. In a further aspect, a dielectric insulator is positioned between the first and second chips and positioned on a base of the package. In still a further aspect, a semiconductor chip with a photosensitive device formed therein includes at least one optical layer positioned on the photosensitive device. A plurality of bond pads are positioned on the chip that are electrically coupled to the photosensitive device on the chip. Castellations extend outwardly from the bond pads to form a plurality of leadless input/output locations for the package.